A MIPS CPU built from scratch, ten instructions, with a self-checking testbench for every module. Pipelining next.
Han Wang
Auckland, New Zealand
Electrical and Electronic Engineering student at the University of Auckland, focused on digital hardware design.
Featured project
Approximate-Arithmetic FPGA Accelerator
- Parameterised approximate multiplier in Verilog, explored across truncation and bit-width.
- MAC unit and 2×2 systolic array with on-chip weight memory.
- ~40% less single-multiply error from an original de-bias correction.
- Deployed on a Zynq-7020 over a UART written from scratch.
Projects
Smart Power Bank
Firmware for a bidirectional buck-boost power bank, with fault protection that holds even if the firmware locks up.
Zynq Sine-Wave Filter
Streamed noisy data from the ARM core to the FPGA fabric and cleaned it with a moving-average filter.
Experience
Lab supervision, marking and test invigilation.
Protection and secondary design for distribution substations, working to IEC and ANSI standards.
Taught over 750 weekly one-to-one lessons.
Delivery Driver
Contract work over the university summer break.
Education
BE(Hons), Electrical & Electronic Engineering
Cumulative GPA 8.71 / 9. Dean's Honours List in 2024 and 2025.
Awards & Scholarships
- Students' Choice Award, ECSE Design CompetitionJul 2026
- Energy Education Trust ScholarshipMay 2026
- Aruhiko Power Engineering ScholarshipMay 2026
- Runners-up, NZ Engineering Science CompetitionNov 2023
Skills
- Hardware description
- Verilog, SystemVerilog
- FPGA & EDA
- Vivado, Vitis, Icarus Verilog
- Programming
- C, Python, Java, MATLAB
- Tools
- Git, LTspice, PLECS, Altium Designer